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EL5126
Data Sheet August 24, 2006 FN7337.2
8-Channel TFT-LCD Reference Voltage Generator
The EL5126 is designed to produce the reference voltages required in TFT-LCD applications. Each output is programmed to the required voltage with 10 bits of resolution. Reference pins determine the high and low voltages of the output range, which are capable of swinging to either supply rail. Programming of each output is performed using the serial interface. A number of the EL5126 can be stacked for applications requiring more than 8 outputs. The reference inputs can be tied to the rails, enabling each part to output the full voltage range, or alternatively, they can be connected to external resistors to split the output range and enable finer resolutions of the outputs. The EL5126 has 8 outputs and is available in a 32 Ld QFN package. It is specified for operation over the full -40C to +85C temperature range.
Features
* 8-channel reference outputs * Accuracy of 0.1% * Supply voltage of 4.5V to 16.5V * Digital supply 3.3V to 5V * Low supply current of 10mA * Rail-to-rail capability * I2C control interface
Applications
* TFT-LCD drive circuits * Reference voltage generators
Pinout
EL5126 (32 LD 5X6 QFN) TOP VIEW
32 OSC_SEL 28 STD/REG 27 FILTER
Ordering Information
PART NUMBER EL5126CL EL5126CLZ (Note) EL5126CL-T7 EL5126CLZ-T7 (Note) EL5126CL-T13 EL5126CLZ-T13 (Note) PART MARKING PACKAGE 5126CL 5126CLZ 5126CL 5126CLZ 5126CL 5126CLZ 32 Ld QFN 32 Ld QFN (Pb-free) 32 Ld QFN 32 Ld QFN (Pb-free) 32 Ld QFN 32 Ld QFN (Pb-free) TAPE AND REEL 7" 7" 13" 13" PKG. NO. MDP0046
VSD 2
31 OSC
30 SDA
29 SCL
VS 1
26 NC 25 OUTA 24 OUTB 23 OUTC 22 OUTD 21 DGND 20 OUTE 19 OUTF 18 OUTG 17 OUTH NC 16
MDP0046
VS 3
MDP0046 MDP0046 MDP0046 MDP0046
REFH 4 REFL 5 AGND 6 CAP 7 NC 8 VS 9 A0 10 NC 12 DGND 13 NC 14 DGND 11 NC 15 THERMAL PAD
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL5126
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . .+18V Supply Voltage between VSD and GND . . . . . . . . . . . . . . . . . . .+7V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY IS ISD ANALOG VOL VOH ISC PSRR tD VAC VDROOP RINH REG DIGITAL VIH VIL FCLK RSDIN tS tH tR tF Supply Current
VS = 18V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = +25C Unless Otherwise Specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
No load
7.6 1.9
9 3.2
mA mA
Digital Supply Current
Output Swing Low Output Swing High Short Circuit Current Power Supply Rejection Ratio Program to Out Delay Accuracy Droop Voltage Input Resistance @ VREFH, VREFL Load Regulation
Sinking 5mA Sourcing 5mA RL = 10 VS+ is moved from 14V to 16V 14.85 150 45
50 14.95 240 60 4 20
150
mV V mA dB ms mV
FCLOCK = 25kHz
1 32
2
mV/ms k
IOUT = 5mA step
0.5
1.5
mV/mA
Logic 1 Input Voltage
VSD20% 20%* VSD 400 1 40 40 20 20
V
Logic 0 Input Voltage
V
Clock Frequency SDIN Input Resistance Setup Time Hold Time Rise Time Fall Time
kHz G ns ns ns ns
2
EL5126 Pin Descriptions
PIN NUMBER 1, 3, 9 2 4 5 6, 21, 11, 13 7 8, 12, 14, 15, 16, 26 10 17 18 19 20 22 23 24 25 27 28 29 30 31 32 PIN NAME VS VSD REFH REFL GND CAP NC A0 OUTH OUTG OUTF OUTE OUTD OUTC OUTB OUTA FILTER STD/REG SCL SDA OSC OSC_SEL Logic Input Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Logic Input Logic Input Logic Input Logic Input IP/OP Logic Input Development I2C address input, bit 0 Channel H programmable output voltage Channel G programmable output voltage Channel F programmable output voltage Channel E programmable output voltage Channel D programmable output voltage Channel C programmable output voltage Channel B programmable output voltage Channel A programmable output voltage Activates internal I2C data filter, high = enable, low = disable Selects mode, high = standard, low = register mode I2C clock I2C data input Oscillator pin for synchronizing multiple chips Selects internal/external OSC source, high = external, low = internal PIN TYPE Power Power Analog Input Analog Input Power Analog PIN DESCRIPTION Positive power supply for analog circuits Positive power supply for digital circuits High reference voltage Low reference voltage Ground Decoupling capacitor for internal reference generator
Typical Performance Curves
DIFFERENTIAL NONLINEARITY (LSB)
0.3 0.2 0.1 IS (mA) 0 -0.1 -0.2 -0.3 10 VS=15V VSD=5V VREFH=13V VREFL=2V 210 410 610 810 1010
7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 INPUT CODE 4
ALL CHANNEL OUTPUT = 0V
6
8
10 12 VS (V)
14
16
18
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. SUPPLY VOLTAGE vs SUPPLY CURRENT
3
EL5126 Typical Performance Curves (Continued)
1.2 VS=VREFH=15V 1.0 VREFL=0V 0mA 0.8 ISD (mA) 0.6 0.4 0.2 0 3 3.2 3.4 3.5 3.8 4 4.2 4.4 4.5 4.8 VSD (V) 5 5V 5mA
VS=VREFH=15V M=400ns/DIV 5mA/DIV
CL=4.7nF RS=20 200mV/DIV
CL=1nF RS=20 CL=180pF
FIGURE 3. DIGITAL SUPPLY VOLTAGE vs DIGITAL SUPPLY CURRENT
VS=VREFH=15V M=400ns/DIV 5mA 0mA CL=1nF RS=20
FIGURE 4. TRANSIENT LOAD REGULATION (SOURCING)
5V 0V
SCLK
SDA 5V 0V 10V
CL=4.7nF RS=20 CL=180pF
5V 0V OUTPUT
M=400s/DIV
FIGURE 5. TRANSIENT LOAD REGULATION (SINKING)
FIGURE 6. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V)
SCLK 5V SDA 0V 5V 0V
SCLK
SDA
OUTPUT 200mV OUTPUT 0V M=400s/DIV
M=400s/DIV
FIGURE 7. LARGE SIGNAL RESPONSE (FALLING FROM 8V TO 0V)
FIGURE 8. SMALL SIGNAL RESPONSE (RISING FROM 0V TO 200mV)
4
EL5126 Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - LPP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3 POWER DISSIPATION (W) SCLK 2.857W 2.5
LP J
SDA
2 1.5 1 0.5 0
2 P3 C/W 5 =3
A
OUTPUT
M=400s/DIV
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 9. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 0V)
FIGURE 10. POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 0.8 POWER DISSIPATION (W) 0.7 758mW 0.6
J 2 W P3 C/ LP 32 =1
A
0.5 0.4 0.3 0.2 0.1 0 0 25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 11. POWER DISSIPATION vs AMBIENT TEMPERATURE
General Description
The EL5126 provides a versatile method of providing the reference voltages that are used in setting the transfer characteristics of LCD display panels. The V/T (Voltage/Transmission) curve of the LCD panel requires that a correction is applied to make it linear; however, if the panel is to be used in more than one application, the final curve may differ for different applications. By using the EL5126, the V/T curve can be changed to optimize its characteristics according to the required application of the display product. Each of the eight reference voltage outputs can be set with a 10-bit resolution. These outputs can be driven to within 50mV of the power rails of the EL5126. As all of the output buffers are identical, it is also possible to use the EL5126 for applications other than LCDs where multiple voltage references are required that can be set to 10 bit accuracy.
Digital Interface
The EL5126 uses a simple two-wire I2C digital interface to program the outputs. The bus line SCLK is the clock signal line and bus SDA is the data information signal line. The EL5126 can support the clock rate up to 400kHz. External pull up resistor is required for each bus line. The typical value for these two pull up resistor is about 1k. START AND STOP CONDITION The Start condition is a high to low transition on the SDA line while SCLK is high. The Stop condition is a low to high transition on the SDA line while SCLK is high. The start and stop conditions are always generated by the master. The bus is considered to be busy after the start condition and to be free again a certain time after the stop condition. The two bus lines must be high when the buses are not in use. The I2C Timing Diagram 2 shows the format.
5
EL5126
DATA VALIDITY The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the clock signal on the SCLK line is low. BYTE FORMAT AND ACKNOWLEDGE Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit first (MSB). The master puts a resistive high level on the SDA line during the acknowledge clock pulse. The peripheral that acknowledges has to pull down the SDA line during the acknowledge clock pulse. DEVICES ADDRESS AND W/R BIT Data transfers follow the format shown in Timing Diagram 1. After the Start condition, a first byte is sent which contains the Device Address and write/read bit. This address is a 7bit long device address and only two device addresses (74H and 75H) are allowed for the EL5126. The first 6 bits (A6 to A1, MSBs) of the device address have been factory programmed and are always 111010. Only the least significant bit A0 is allowed to change the logic state, which can be tied to VSD or DGND. A maximum of two EL5126 may be used on the same bus at one time. The EL5126 monitors the bus continuously and waiting for the start condition followed by the device address. When a device recognizes its device address, it will start to accept data. An eighth bit is followed by the device address, which is a data direction bit (W/R). A "0" indicates a Write transmission and a "1" indicates a Read transmission. The EL5126 can be operated as Standard mode and Register mode. See the I2C Timing Diagram 1 for detail formats. STANDARD MODE The part operates at Standard Mode if pin 28 (STD/REG) is held high. The Standard Mode allows the user to program
TABLE 2. REGISTER ADDRESS R3 X X X X R2 0 0 0 1 R1 0 0 1 1 R0 0 1 0 1 D9 0 1 0 1 D8 0 0 0 1 D7 0 0 0 1 D6 0 0 0 1 DATA D5 0 0 0 1 D4 0 0 1 1 D3 0 0 1 1 D2 0 0 1 1 D1 0 0 1 1 D0 0 0 1 1 CONDITION Channel A, Value = 0 Channel B, Value = 512 Channel C, Value = 31 Channel H, Value = 1023
the eight outputs at one time. Two data bytes are required for 10-bit data for each channel output and there are total of 16 data bytes for 8 channels. Data in data byte 1 and 2 is for channel A. Data in data byte 15 and 16 is for channel H. D9 to D0 are the 10-bit data for each channel. The unused bits in the data byte are "don't care" and can be set to either one or zero. See Table 1 for program sample for one channel setting:
TABLE 1. DATA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CONDITION Data value = 0 Data value = 512 Data value = 31 Data value = 1023
When the W/R bit is high, the master can read the data from the EL5126. See Timing Diagram 1 for detail formats. REGISTER MODE The part operates at Register Mode if pin 28 (STD/REG) is held low. The Register Mode allows the user to program each output individually. Followed by the first byte, the second byte sets the register address for the programmed output channel. Bits R0 to R3 set the output channel address. For the unused bits in the R4 to R7 are "don't care". See Table 2 for program sample. The EL5126 also allows the user to read the data at Register Mode. See Timing Diagram 1 for detail formats. DIGITAL FILTER A user selectable digital filter can be used to filter noise spikes from the SCLK and SDA inputs. When the Filter pin (pin27) is high, the digital filter is enabled. When the Filter pin is low, the digital filter is disabled.
6
I2C Timing Diagram 1
STANDARD MODE (STD/REG = HIGH) WRITE MODE I2C Data I2C Data In I2C CLK In Start Device Address WA = don't care Data 1 A Data 2 A Data 3 Data 16 A Stop
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5
D2 D1 D0
12345678
12345678
12345678
678
7
STANDARD MODE (STD/REG = HIGH) READ MODE I2C Data I2C Data In I2C Data Out I2C CLK In Start Device Address RA Data 1 A Data 2 A Data 3 Data 16 NA Stop A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D2 D1 D0
EL5126
12345678
12345678
12345678
678
REGISTER MODE (STD/REG = LOW) WRITE MODE I2C Data I2C Data In I2C CLK In Start Device Address WA Register Address A Data 1 A Data 2 A Stop
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 R3 R2 R1 R0
D7 D6 D5 D4 D3 D2 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
12345678
12345678
12345678
12345678
REGISTER MODE (STD/REG = LOW) READ MODE I2C Data I2C Data In I2C Data Out Start Device Address WA Register Address A Start Device Address RA Data 1 A Data 2 NA Stop
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 R3 R2 R1 R0
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
I2C CLK In
12345678
12345678
12345678
12345678
12345678
EL5126 I2C Timing Diagram 2
START CONDITION tF STOP CONDITION
tR
positive than the VCOM potential. The second EL5126 can provide the Gamma correction voltage more negative than the VCOM potential. The Application Drawing shows a system connected in this way. CLOCK OSCILLATOR
DATA
CLOCK tS tH tS tH tR tF
START, STOP & TIMING DETAILS OF I2C INTERFACE
Analog Section
TRANSFER FUNCTION The transfer function is:
data V OUT ( IDEAL ) = V REFL + ------------ x ( V REFH - V REFL ) 1024
The EL5126 requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn't be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labeled OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the OSC pin. In a 2 chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source. For transient load application, the external clock Mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will start with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. By setting pin 32 to high, the chip is on external clock mode. Setting pin 32 to low, the chip is on internal clock mode.
where data is the decimal value of the 10-bit data binary input code. The output voltages from the EL5126 will be derived from the reference voltages present at the VREFL and VREFH pins. The impedance between those two pins is about 32k. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5126. GND < VREFH VS and GND VREFL VREFH. In some LCD applications that require more than 8 channels, the system can be designed such that one EL5126 will provide the Gamma correction voltages that are more
8
EL5126 Block Diagram
REFERENCE HIGH
OUT
OUT
OUT
OUT
EIGHT CHANNEL MEMORY
OUT VOLTAGE SOURCES OUT
OUT
OUT
REFERENCE LOW REFERENCE DECOUPLE I2C DATA IN I2C CLOCK IN CONTROL IF
FILTER
STD/REG
A0
OSCILLATOR OSCILLATOR INPUT/OUTPUT SELECT
CHANNEL OUTPUTS Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 100mV of the power rails, (see Electrical Characteristics for details). When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5 and 50). Each of the channels is updated on a continuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. The best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 48s. In the worst-case scenario this will be 380s, when the data has just missed the cycle. When a large change in output voltage is required, the change will occur in 2V steps, thus the requisite number of timing cycles will be added to the overall update time. This means that a large change of 16V can take between 3ms and 3.4ms depending on the absolute timing relative to the update cycle. 9
POWER DISSIPATION With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package
EL5126
The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads.
P DMAX = V S x I S + [ ( V S - V OUT i ) x I LOAD i ]
POWER SUPPLY BYPASSING AND PRINTED CIRCUIT BOARD LAYOUT Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5126. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5126 should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1F ceramic capacitor must be place very close to the VS, VREFH, VREFL, and CAP pins. A 4.7F local bypass tantalum capacitor should be placed to the VS, VREFH, and VREFL pins. APPLICATION USING THE EL5126 In the first application drawing, the schematic shows the interconnect of a pair of EL5126 chips connected to give 8 gamma corrected voltages above the VCOM voltage, and 8 gamma corrected voltages below the VCOM voltage.
when sourcing, and:
P DMAX = V S x I S + ( V OUT i x I LOAD i )
when sinking. Where: * i = 1 to total 8 * VS = Supply voltage * IS = Quiescent current * VOUTi = Output voltage of the i channel * ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, we can solve for the RLOAD's to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat.
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EL5126 Application Drawing
HIGH REFERENCE VOLTAGE +10V 0.1F +12V 0.1F MICROCONTROLLER +5V 0.1F VSD FILTER OUTD AO I2C DATA IN I2C CLOCK LCD TIMING CONTROLLER HORIZONTAL RATE +5V SDA OUTE SCL OSC OSC_SEL OUTF CAP ADDRESS = H74 OUTC VS OUTB REFH OUTA
COLUMN (SOURCE) DRIVER
LCD PANEL
0.1F OUT REFL STD GND
OUTH
EL5126 +5.5V MIDDLE REFERENCE VOLTAGE
+5V +12V 0.1F
OUTA REFH OSC OSC_SEL VS OUTB
+5V 0.1F I2C DATA IN I2C CLOCK
VSD FILTER AO SDA SCL CAP
OUTC
OUTD
OUTE
ADDRESS = H75
+1V
0.1F LOW REFERENCE VOLTAGE 0.1F
OUTF REFL OUT STD GND
OUTH
EL5126
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
EL5126 QFN (Quad Flat No-Lead) Package Family
A D N (N-1) (N-2) B
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) SYMBOL QFN44 QFN38 A A1 0.90 0.02 0.25 0.20 7.00 5.10 7.00 5.10 0.50 0.55 44 11 11 0.90 0.02 0.25 0.20 5.00 3.80 7.00 5.80 0.50 0.40 38 7 12 QFN32 0.90 0.02 0.23 0.20 8.00 0.90 0.02 0.22 0.20 5.00 TOLERANCE 0.10 +0.03/-0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference NOTES 8 8 4 6 5
1 2 3
b
PIN #1 I.D. MARK E
c D D2 E E2
(N/2)
5.80 3.60/2.48 8.00 6.00
5.80 4.60/3.40 0.80 0.53 32 8 8 0.50 0.50 32 7 9
2X 0.075 C
e
2X 0.075 C
L N ND NE
TOP VIEW N LEADS
0.10 M C A B (N-2) (N-1) N b
L
PIN #1 I.D. 3 1 2 3
SYMBOL QFN28 QFN24 A A1 b 0.90 0.02 0.25 0.20 4.00 2.65 5.00 3.65 0.50 0.40 28 6 8 0.90 0.02 0.25 0.20 4.00 2.80 5.00 3.80 0.50 0.40 24 5 7
QFN20 0.90 0.02 0.30 0.20 5.00 3.70 5.00 3.70 0.65 0.40 20 5 5 0.90 0.02 0.25 0.20 4.00 2.70 4.00 2.70 0.50 0.40 20 5 5
QFN16 0.90 0.02 0.33 0.20 4.00 2.40 4.00 2.40 0.65 0.60 16 4 4
TOLERANCE NOTES 0.10 +0.03/ -0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference 4 6 5
(E2)
c D
NE 5 (N/2)
D2 E E2
(D2) BOTTOM VIEW
7
e L N
e C SEATING PLANE 0.08 C N LEADS & EXPOSED PAD
0.10 C
ND NE NOTES:
Rev 10 12/04 1. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL "X" SIDE VIEW
2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the "E" side of the package (or Y-direction).
(c) C A
2
6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE.
(L)
7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet.
A1 DETAIL X
N LEADS
12

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